STM8S datasheet(196/467 Pages) STMICROELECTRONICS

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16-bit advanced control timer (TIM1)

RM0016

196/467

DocID14587 Rev 14

17.7.7

Status register 2 (TIM1_SR2)

Address offset: 0x06

Reset value: 0x00

Bit 2 CC2IF: Capture/compare 2 interrupt flag

Refer to CC1IF description

Bit 1 CC1IF: Capture/compare 1 interrupt flag

If channel CC1 is configured as output:

This flag is set by hardware when the counter matches the compare value, with some exception in

center-aligned mode (refer to the CMS bits from TIM1_CR1 register description). It is cleared by

software.

0: No match

1: The content of the counter register TIM1_CNT matches the content of the TIM1_CCR1 register

Note: When the contents of TIMx_CCRi are greater than the contents of TIMx_ARR, the CCiIF bit

goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow

(in down-counting mode)

If channel CC1 is configured as input:

This bit is set by hardware on a capture. It is cleared by software or by reading the TIM1_CCR1L

0: No input capture has occurred

1: The counter value has been captured in the TIM1_CCR1 register (an edge has been detected on

IC1 which matches the selected polarity).

Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update has occurred

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

–

At overflow or underflow if UDIS = 0 in the TIM1_CR1 register

–

When CNT is re-initialized by software using the UG bit in TIM1_EGR register, if URS = 0

and UDIS = 0 in the TIM1_CR1 register.

–

When CNT is re-initialized by a trigger event (refer to the TIM1_SMCR register description),

if URS = 0 and UDIS = 0 in the TIM1_CR1 register.

654

3210

Reserved

CC4OF

CC3OF

CC2OF

CC1OF

Reserved

rc_w0

Bits 7:5 Reserved, must be kept cleared

Bit 4 CC4OF: Capture/compare 4 overcapture flag

Refer to CC1OF description

Bit 3 CC3OF: Capture/compare 3 overcapture flag

Refer to CC1OF description

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