STM8S datasheet(172/467 Pages) STMICROELECTRONICS

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16-bit advanced control timer (TIM1)

RM0016

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DocID14587 Rev 14

Figure 68. Detailed output stage of channel with complementary output (channel 1)

17.5.5

Forced output mode

In output mode (CCiS bits = 00 in the TIM1_CCMRi registers), each output compare signal

can be forced to high or low level directly by software, independently of any comparison

between the output compare register and the counter.

To force an output compare signal to its active level, write 101 in the OCiM bits in the

corresponding TIM1_CCMRi registers. OCiREF is forced high (OCiREF is always active

high) and the OCi output is forced high or low depending on the CCiP polarity bits.

For example, if CCiP = 0 (OCi active high) => OCi is forced high.

The OCiREF signal can be forced low by writing the OCiM bits to 100 in the TIMx_CCMRx

registers.

Nevertheless, the comparison between the TIM1_CCRi shadow registers and the counter is

still performed and allows the flag to be set. Interrupt requests can be sent accordingly. This

is described in the output compare mode section below.

17.5.6

Output compare mode

This function is used to control an output waveform or indicate when a period of time has

elapsed.

When a match is found between the capture/compare register and the counter:

•

Depending on the output compare mode, the corresponding OCi output pin:

–

Keeps its level (OCiM = 000),

–

Is set active (OCiM = 001),

–

Is set inactive (OCiM = 010)

–

Toggles (OCiM = 011)

•

A flag is set in the interrupt status register (CCiIF bits in the TIM1_SR1 register).

•

An interrupt is generated if the corresponding interrupt mask is set (CCiIE bits in the

TIM1_IER register).

STM8S Datasheet(PDF) 172 Page - STMicroelectronics