STM8S datasheet(156/467 Pages) STMICROELECTRONICS

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16-bit advanced control timer (TIM1)

RM0016

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DocID14587 Rev 14

Trigger reset mode

The counter and its prescaler can be re-initialized in response to an event on a trigger input.

Moreover, if the URS bit from the TIM1_CR1 register is low, a UEV is generated. Then all

the preloaded registers (TIM1_ARR, TIM1_CCRi) are updated.

Example

Use the following procedure to clear the up-counter in response to a rising edge on TI1

input:

Configure channel 1 to detect rising edges on TI1. As no filter is required in this

example, configure an input filter duration of 0 (IC2F = 0000). The capture prescaler is

not used for triggering and does not need to be configured. The CC1S bits select the

input capture source and do not need to be configured either. Write CC1P = 0 in

TIM1_CCER1 register to validate the polarity (and detect rising edges).

Configure the timer in reset mode by writing SMS = 100 in TIM1_SMCR register. Select

TI1 as the input source by writing TS = 101 in the TIM1_SMCR register.

Start the counter by writing CEN = 1 in the TIM1_CR1 register.

The counter starts counting on the internal clock and behaves normally until the TI1 rising

edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the

trigger flag is set (TIF bit in the TIM1_SR1 register) and an interrupt request can be sent if

enabled (depending on the TIE in the TIM1_IER register).

Figure 50 shows this behavior when the auto-reload register TIM1_ARR = 36h. The delay

between the rising edge on TI1 and the actual reset of the counter is due to the

resynchronization circuit on TI1 input.

Figure 50. Control circuit in trigger reset mode

STM8S Datasheet(PDF) 156 Page - STMicroelectronics