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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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STR720 Datasheet(PDF) 164 Page - STMicroelectronics |
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STR720 Datasheet(HTML) 164 Page - STMicroelectronics |
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164 / 401 page  STR720 - ASYNCHRONOUS AHB-APB BRIDGE (A3BRG) 164/401 Peripherals Address Error Register (PAER) Address Offset: 08h Reset value: 0x0000_0000 Bit 31:25 = Reserved. These bits must be always written to and read back as ‘0’. Bit 24= nRW: access type. It returns the type of access that generate the error conditions: read(0) or write(1) Bit 23:0 = Peripheral Address. The Bridge is able to detect some errors while accessing to a peripherals. If an error occurs, the bridge ends the APB transaction and reports on the AHB bus an ERROR condition (if enabled). The address of slave generating the error condition is reported in the PERIPHERAL ADDRESS field. Depending of the size of the AHB addressing space, the MSB can be filled with 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved nRW Peripheral Address (23:16) - r rrrrrr r r 15 14 13 12 11 10 9 8 765432 1 0 Peripheral Address (15:0) rrrrrr r r rrrrrr r r 1 |
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