HD64F2145 datasheet(119/829 Pages) RENESAS

No. de pieza	HD64F2145

Descripción Electrónicos	Hitachi 16-Bit Single-Chip Microcomputer

PDF	829 Pages

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Fabricante Electrónico	RENESAS [Renesas Technology Corp]

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119 / 829 page

Rev. 2.0, 08/02, page 79 of 788

Section 4 Exception Handling

4.1

Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or

trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions

occur simultaneously, they are accepted and processed in order of priority.

Table 4.1

Exception Types and Priority

Priority

Exception Type

Start of Exception Handling

Reset

Starts immediately after a low-to-high transition of the

5(6

pin, or when the watchdog timer overflows.

Interrupt

Starts when execution of the current instruction or exception

handling ends, if an interrupt request has been issued.

Interrupt detection is not performed on completion of ANDC,

ORC, XORC, or LDC instruction execution, or on

completion of reset exception handling.

High

Direct transition

Starts when a direction transition occurs as the result of

SLEEP instruction execution.

Low

Trap instruction

Started by execution of a trap (TRAPA) instruction. Trap

instruction exception handling requests are accepted at all

times in program execution state.

HD64F2145 Datasheet(PDF) 119 Page - Renesas Technology Corp