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ATMEGA328P Datasheet(PDF) 9 Page - ATMEL Corporation |
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ATMEGA328P Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 294 page 9 ATmega328P [DATASHEET] 7810D–AVR–01/15 6. AVR CPU Core 6.1 Overview This section discusses the AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 6-1. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system reprogrammable flash memory. Status and Control Interrupt Unit 32 x 8 General Purpose Registers ALU Data Bus 8-bit Data SRAM SPI Unit Instruction Register Instruction Decoder Watchdog Timer Analog Comparator EEPROM I/O Lines I/O Module n Control Lines I/O Module 2 I/O Module 1 Program Counter Flash Program Memory |
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