DSP56857 datasheet(202/662 Pages) FREESCALE

202 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

8-24

Freescale Semiconductor

8.7.9 Interrupt Priority Register 8 (IPR8)

Figure 8-11. Interrupt Priority Register 8 (IPR8)

8.7.9.1 Reserved—Bits 15–10

These bits are reserved or not implemented. They are read as 0, but cannot be modified by

writing.

8.7.9.2 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)—Bits 9–8

These fields are used to set the interrupt priority levels for certain peripheral IRQs. These IRQs

are limited to priorities zero through two and are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

8.7.9.3 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)—Bits 7–6

These fields are used to set the interrupt priority levels for certain peripheral IRQs. These IRQs

are limited to priorities zero through two and are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

Base + $8

Read

SCI1_RCV

IPL

SCI1_RERR

IPL

SCI1_RIDL

IPL

SCI1_TIDL

IPL

SCI1_XMIT

IPL

Write

Reset

000

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