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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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DSP56857 Datasheet(PDF) 163 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 163 Page - Freescale Semiconductor, Inc |
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163 / 662 page  Register Descriptions (CGM_BASE = $1FFF10) On-Chip Clock Synthesis (OCCS), Rev. 4 Freescale Semiconductor 6-13 start the count again. The lock detector is designed so if LCK1 is reset to 0 because the counts did not match when checked after 64 cycles, the LCK0 bit can remain high if the counts matched after 32 cycles. This provides the processor the accuracy of the two clocks with respect to each other. 6.5 Module Memory Map There are three registers on the CGM peripheral described in Table 6-1. 6.6 Register Descriptions (CGM_BASE = $1FFF10) 6.6.1 Clock Generation Module (CGM) Control Register Figure 6-9. CGM Control Register (CGMCR) See Programmer’s Sheet on Appendix page B-14 6.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing. Table 6-1. CGM Memory Map $1FFF10 Address Offset Register Acronym Register Name Access Type Chapter Location Base + $0 CGMCR Control Register Read/Write Section 6.6.1 Base + $1 CGMDB Divide-By Register Read/Write Section 6.6.2 Base + $2 CGMTOD Time-of-Day Register Read/Write Section 6.6.3 Add. Offset Register Name 15 14 13 12 11 10 9876 54321 0 $0 CGMCR R 0 0 LCK1 LCK0 SEL 0 0 0 0 LCK1_IE LCK0_IE LCK ON TOD_ SEL PDN W $1 CGMDB R POST 0 0 0 0 0 0 PLLDB W $2 CGMTOD R 0 0 0 0 TOD W R 0 Read as 0 W Reserved Figure 6-8. OCCS Register Map Summary Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 LCK1 LCK0 SEL 0 0 0 0 LCK1_IE LCK0_IE LCKON TOD_SEL PDN Write Reset 00 0 0 0 0 00 0 0 0 0 0 0 0 1 |
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