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DSP56857 Datasheet(PDF) 336 Page - Freescale Semiconductor, Inc

No. de pieza DSP56857
Descripción Electrónicos  Digitial Signal Controller
PDF  662 Pages
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Fabricante Electrónico  FREESCALE [Freescale Semiconductor, Inc]
Página de inicio  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 336 Page - Freescale Semiconductor, Inc

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Register Descriptions (ESSI0_BASE = $1FFE20, ESSI1_BASE = $1FFE00)
5685X Digital Signal Controller User Manual, Rev. 4
12-36
Freescale Semiconductor
Figure 12-21. Frame Sync Timing Options
12.8.7.15 Receive FIFO Full (RFF)—Bit 1
This flag bit is set when the receive section is programmed with the enabled Receive FIFO. The
data level in the RXFIFO must reach the selected Receive FIFO Watermark (RFWM) threshold.
When set, the RFF indicates data can be read using the SRX register.
Note:
An interrupt is generated only if both RFF and RIE bits are set and if the RXFIFO is
enabled.
The RFF bit is cleared in normal operation by reading the SRX register. The RFF is cleared by
Power-On Reset (POR) or disabling the ESSI (ESSIEN = 0). When the RXFIFO is completely
full, all further received data is ignored until current data is read.
TS 0
TS 1
TS n
a) Frame Sync Timing Options
b) TFS Status Flag Operation
c) RFS Status Flag Operation
SCK, SC0
Bit-Length FS
Early Bit-Length FS
Word-Length FS
Early Word-Length FS
Time Slots
STX Register
TFS
STD Pin
SRD Pin
RFS
SRX Register
Indefinite transition depends on SW interrupt processing
Invalid
Valid



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