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MSP432P411VIPZ Datasheet(PDF) 151 Page - Texas Instruments |
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MSP432P411VIPZ Datasheet(HTML) 151 Page - Texas Instruments |
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151 / 212 page ![]() Py.x/USCI/Lz PySEL1.x PyDIR.x PyIN.x EN To USCI From USCI PyOUT.x 1 0 DVSS DVCC 1 D Lz LCDSz Pad Logic Bus Keeper Direction 0: Input 1: Output PyREN.x 0 1 0 0 1 0 1 1 PySEL0.x 0 1 0 0 1 0 1 1 DVSS From USCI DVSS 151 MSP432P4111, MSP432P4011, MSP432P411Y MSP432P401Y, MSP432P411V, MSP432P401V www.ti.com SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018 Submit Documentation Feedback Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V Detailed Description Copyright © 2017–2018, Texas Instruments Incorporated 6.12 Input/Output Diagrams 6.12.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger Figure 6-8 shows the port schematic. Table 6-63 lists the settings to select the port functions. Functional representation only. Figure 6-8. Py.x/USCI/Lz Port Schematic |
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