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DS31256 Datasheet(PDF) 155 Page - Maxim Integrated Products |
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DS31256 Datasheet(HTML) 155 Page - Maxim Integrated Products |
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155 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 155 of 183 11.3Examples of Bus Timing for Local Bus PCI Bridge Mode Operation Figure 11-5. 8-Bit Read Cycle Intel Mode (LIM = 0) Arbitration Enabled (LARBE = 1) Bus Transaction Time = 4 LCLK (LRDY = 0100) An attempted access by the host causes the local bus to request the bus. If bus access has not been granted ( LBGACK deasserted), the timing shown at the top of the page applies, with LHOLD being asserted. Once LHLDA is detected, the local bus grabs the bus for 32 to 1,048,576 clocks and then releases it. If the bus has already been granted ( LBGACK asserted), the timing shown at the bottom of the page applies. LCLK LHOLD LHLDA LBGACK 32 to 1,048,576 LCLKs LA[19:0] LD[7:0] LD[15:8] LRD LWR Address Valid LBHE Tri-state Tri-State Tri-State Tri-State LCLK 12 34 Note: LA, LD, LBHE, LWR, and LRD are tri-stated. |
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