1FEATURES
2• 20 to 65 MHz Shift Clock Support
• 50% Duty Cycle on Receiver Output Clock
• Best-in-Class Set & Hold Times on
RxOUTPUTs
• Rx Power Consumption <142 mW (typ)
@65MHz Grayscale
• Rx Power-down Mode <200μW (max)
• ESD Rating >7 kV (HBM), >700V (EIAJ)
• Supports VGA, SVGA, XGA and Dual Pixel
SXGA.
• PLL Requires no External Components
• Compatible with TIA/EIA-644 LVDS Standard
• Low Profile 56-lead or 48-lead Packages

DESCRIPTION
The DS90CF384A receiver converts the four LVDS
data streams (Up to 1.8 Gbps throughput or 227
Megabytes/sec bandwidth) back into parallel 28 bits
of CMOS/TTL data (24 bits of RGB and 4 bits of
Hsync, Vsync, DE and CNTL). Also available is the
DS90CF364A that converts the three LVDS data
streams (Up to 1.3 Gbps throughput or 170
Megabytes/sec bandwidth) back into parallel 21 bits
of CMOS/TTL data (18 bits of RGB and 3 bits of
Hsync, Vsync and DE). Both Receivers' outputs are
Falling edge strobe. A Rising edge or Falling edge
strobe transmitter (DS90C383A/DS90C363A) will
interoperate with a Falling edge strobe Receiver
without any translation logic.
The DS90CF384A / DS90CF364A devices are
enhanced over prior generation receivers and
provided a wider data valid time on the receiver
output.
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.